1. Field of the Invention
The present invention relates to a failure analysis system automatically extracting fatal failures of a semiconductor wafer formed with a plurality of chips each having a plurality of memory cells.
2. Description of the Background Art
As a failure analysis method for a semiconductor wafer formed with a plurality of semiconductor chips having a plurality of memory cells, generally arranged in the form of a matrix specified by rows and columns, a method employing a tester (also referred to as an LSI tester) is generally known. According to this method, all memory cells in the semiconductor wafer are tested in relation to electric characteristics so that memory cell failures detected as a result are displayed in a coordinate space defined by x-coordinates along the row direction and y-coordinates along the column direction in the form of failure patterns (generally a fail bit map, hereinafter abbreviated as FBM) for estimating the failure factors with the FBM.
In general, a semiconductor chip having a plurality of memory cells has redundancy (substitute) memory cells for repairing faulty memory cells, and can repair faulty memory cells in a range repairable with the redundancy memory cells. Therefore, failures in the semiconductor chip having a plurality of memory cells can be classified into repairable failures and unrepairable failures. The repairable failures and the unrepairable failures can be regarded as failures exerting no influence on the yield and fatal failures lowering the yield respectively. It is extremely important to know what kind of failures the unrepairable failures (hereinafter also referred to as fatal failures) are, in order to perform failure analysis of a semiconductor wafer formed with a plurality of semiconductor chips each having a plurality of memory cells.
In order to know what kind of failures the aforementioned fatal failures are, however, a failure analysis engineer merely manually extracts fatal failures from FBM information in general, to disadvantageously require excess time and limit the number of samples.